The Journal of Informational Technology and Applications (JITA) is a scientific journal with an international reach. Its primary goal is to share new ideas, knowledge, and experiences that contribute the development of an information society based on knowledge.Our vision is to become a leading journal that publishes groundbreaking research that advances scientific progress. We invite you to collaborate by submitting original research works related to emerging issues in your field that align with our editorial policies.The journal is published twice a year, in June and December. The deadline for the June issue is April 15th; for the December issue, it is October 15th. After a blind review and evaluation process, authors will be notified of the publishing decision.
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A PLL or phase-locked loop is a control system that creates an output signal whose phase is related to the phase-locked loop and represents controlled input signal. The goal of this research is to first investigate the functioning of new PLL neural networks and then, in the research section, explore an approach involving the extraction of neural symmetrical voltage components. The architectural characteristics of phase-locked loops (PLLs) typically include capture and lock ranges, bandwidth, and transient response. The new neural PLL architecture offers several advantages, such as low noise performance, reduced silicon area, and compatibility with low supply voltages. However, it may also present disadvantages, including hardware dependency and potential design complexity compared to traditional PLL architectures. Evaluating these factors is crucial, depending on the specific needs of the application.
In this paper, we present the scientific research included in the experimental part where we investigate the performance of the proposed neural PLL, for which experimental comparisons with the conventional PLL in a distorted reference frame are necessary. Structural columns or structural circles will be used for graphic display.
The following research methods and techniques will be applied: instruments, basic methods and data processing procedures – if they are foreseen. What makes this work a scientific research work is a descriptive method that will be used.
To better understand how PLLs work, we propose an original three-phase neural approach for components of the system’s phase and symmetry. The quality of the electricity can be assessed and managed with this framework. Our study shows that the full neural architecture may be applied to three-phase power systems because it is based on DSP supplies. Additionally, we present the performance of the PLL system in a three-phase power supply context. Different regulators, such as PI and RST based on phase logic, are incorporated into the PLL scheme. The results suggest that the neural PLL could make a significant contribution in applications where the quality and efficiency of three-phase power systems are essential.
This paper provides a concise overview of Agile and DevOps methodologies in software engineering. It aims to introduce readers to the fundamental principles of Agile and DevOps, accompanied by brief descriptions and practical examples. The advantages and disadvantages of each methodology are discussed, followed by a comparative analysis highlighting key differences. Understanding these methodologies is crucial in today’s IT landscape, as they are commonly employed in various organizations, impacting project management, team collaboration, and product delivery. This paper serves as a valuable resource for individuals seeking a basic understanding of Agile and DevOps methodologies in software engineering.
A PLL or phase-locked loop is a control system that creates an output signal whose phase is related to the phase-locked loop and represents controlled input signal. The goal of this research is to first investigate the functioning of new PLL neural networks and then, in the research section, explore an approach involving the extraction of neural symmetrical voltage components. The architectural characteristics of phase-locked loops (PLLs) typically include capture and lock ranges, bandwidth, and transient response. The new neural PLL architecture offers several advantages, such as low noise performance, reduced silicon area, and compatibility with low supply voltages. However, it may also present disadvantages, including hardware dependency and potential design complexity compared to traditional PLL architectures. Evaluating these factors is crucial, depending on the specific needs of the application.
In this paper, we present the scientific research included in the experimental part where we investigate the performance of the proposed neural PLL, for which experimental comparisons with the conventional PLL in a distorted reference frame are necessary. Structural columns or structural circles will be used for graphic display.
The following research methods and techniques will be applied: instruments, basic methods and data processing procedures – if they are foreseen. What makes this work a scientific research work is a descriptive method that will be used.
To better understand how PLLs work, we propose an original three-phase neural approach for components of the system’s phase and symmetry. The quality of the electricity can be assessed and managed with this framework. Our study shows that the full neural architecture may be applied to three-phase power systems because it is based on DSP supplies. Additionally, we present the performance of the PLL system in a three-phase power supply context. Different regulators, such as PI and RST based on phase logic, are incorporated into the PLL scheme. The results suggest that the neural PLL could make a significant contribution in applications where the quality and efficiency of three-phase power systems are essential.
jita@apeiron-edu.eu
+387 51 247 925
+387 51 247 975
+387 51 247 912
Pan European University APEIRON Banja Luka Journal JITA Pere Krece 13, P.O.Box 51 78102 Banja Luka, Republic of Srpska Bosnia and Hercegovina
© 2024 Paneuropean University Apeiron All Rights Reserved
jita@apeiron-edu.eu
+387 51 247 925
+387 51 247 975
+387 51 247 912
Pan European University APEIRON Banja Luka Journal JITA Pere Krece 13, P.O.Box 51 78102 Banja Luka, Republic of Srpska Bosnia and Hercegovina
© 2024 Paneuropean University Apeiron All Rights Reserved
Pan European University APEIRON Banja Luka Journal JITA Pere Krece 13, P.O.Box 51 78102 Banja Luka, Republic of Srpska Bosnia and Hercegovina
jita@apeiron-edu.eu
+387 51 247 925
+387 51 247 975
+387 51 247 912
© 2024 Paneuropean University Apeiron All Rights Reserved